The invention relates generally to integrated circuits, and more particularly to integrated circuit input/output designs.
Multi-chip and even board level processing has and continues to be increasingly implemented as integrated circuitry on a single chip, with the single chip sometimes referred to as a system-on-chip (SOC). SOCs may send to and receive signals from a variety of devices, such as a variety of memory devices, lower level devices, or devices performing very specialized functions. Each type of device, as well as sub-types of each type of device, may require or use interface signals and pathways which must conform to somewhat specific requirements, and these requirements may differ from one another.
The requirements, which often relate to current strength, voltage levels, input and output impedances, and other matters, are generally promulgated by various standards bodies, although some “standards” may be simply de-facto standards or device manufacturer specific. In any event, SOC integrated circuits may be required to provide input/output (I/O) according to requirements of multiple I/O standards, either simultaneously or across different versions of a chip.
The provision of I/O in accordance with multiple standards poses difficulties in chip design. I/O related circuitry is often placed in I/O slots, generally in an I/O ring about a periphery of a device. The use of different I/O slots configured to meet a variety of I/O standards may increase design time. The replacement of I/O slots of one type with I/O slots of another type, for example for a different version of a chip, may necessitate rework outside of the I/O slot, as well as reverification of significant portions of the design. Moreover, the use of a variety of I/O slots may require tradeoffs in area and power usage, and may degrade overall chip performance
Further complicating matters, I/O sections are often designed at different times, obtained from IP vendors, or integrated into multiple chips. In general, therefore each I/O slot is self-contained. Accordingly, each I/O pad may require its own power structure, electrostatic discharge (ESD) structure, reference current and voltage and calibration. Unfortunately, complex interfaces, design inefficiency and performance degradation may result. For example, each I/O slot may require unique power structures, unique busses, and, possibly, unique power pads. In addition, often additional silicon area is required for developing different voltage references, increasing area and power usage, or the number of voltage references may be reduced, degrading chip performance.
Moreover, calibration circuitry to provide appropriate I/O operation over process, voltage, and temperature variations (PVT) may be required to be duplicated for each different type of I/O slot, increasing design complexity and area and power requirements. Alternatively, calibration circuitry may be reduced or eliminated, and, for example, output circuit drivers may be enhanced so as to always provide a specified minimum current. Such a solution, unfortunately, results in excess current being provided during normal operation, resulting in increased power usage.